Philips Semiconductors
Product specification
Dual N-channel enhancement mode
TrenchMOS
TM
transistor
FEATURES
• Dual device
• Low threshold voltage
• Fast switching
• Logic level compatible
• Surface mount package
PHN210T
SYMBOL
d1 d1
d2 d2
QUICK REFERENCE DATA
V
DS
= 30 V
I
D
= 3.4 A
R
DS(ON)
≤
100 mΩ (V
GS
= 10 V)
R
DS(ON)
≤
200 mΩ (V
GS
= 4.5 V)
s1
g1
s2 g2
GENERAL DESCRIPTION
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using ’trench’
technology.
Applications:-
• Motor and relay drivers
• d.c. to d.c. converters
• Logic level translator
The PHN210T is supplied in the
SOT96-1 (SO8) surface mounting
package.
PINNING
PIN
1
2
3
4
5,6
7,8
DESCRIPTION
source 1
gate 1
source 2
gate 2
drain 2
drain 1
SOT96-1
8
7
6
5
pin 1 index
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Repetitive peak drain-source
voltage
Continuous drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current per MOSFET
1
Drain current per MOSFET (both
MOSFETs conducting)
1
Drain current per MOSFET (pulse
peak value)
Total power dissipation (either or
both MOSFETs conducting)
1
Storage & operating temperature
CONDITIONS
T
j
= 25 ˚C to 150˚C
R
GS
= 20 kΩ
T
a
= 25 ˚C
T
a
= 70 ˚C
T
a
= 25 ˚C
T
a
= 70 ˚C
T
a
= 25 ˚C
T
a
= 25 ˚C
T
a
= 70 ˚C
MIN.
-
-
-
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
30
±
20
3.4
2.8
2.4
1.9
14
2
1.3
150
UNIT
V
V
V
V
A
A
A
A
A
W
W
˚C
1
Surface mounted on FR4 board, t
≤
10 sec
March 1999
1
Rev 1.000
PHILIPS [ NXP SEMICONDUCTORS ]
