NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 kΩ typ.) to V
DD
. The input voltage may be
raised above V
DD
to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either V
DD
or V
SS
.
data from
shift register
configuration
register
data from
shift register
write configuration
pulse
D
FF
CK
Q
D
FF
Q
Q
Q1
100 kΩ
output port
register data
V
DD
IO0 to IO7
write pulse
CK
output port
register
input port
register
D
FF
read pulse
CK
polarity inversion
register
data from
shift register
write polarity
pulse
D
FF
CK
002aac493
Q2
V
SS
Q
input port
register data
to INT
Q
polarity inversion
register data
Remark:
At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of IO0 to IO7
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
9 of 30
PHILIPS [ NXP SEMICONDUCTORS ]
