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PCA9554PW 参数 Datasheet PDF下载

PCA9554PW图片预览
型号: PCA9554PW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位I2C总线和中断的SMBus I / O端口 [8-bit I2C-bus and SMBus I/O port with interrupt]
分类和应用: 并行IO端口微控制器和处理器外围集成电路光电二极管
文件页数/大小: 30 页 / 179 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 6.
Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0*
0*
0*
0*
0*
0*
0*
0*
Description
inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to V
DD
.
Table 7.
Register 3 - Configuration register bit description
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
1*
1*
1*
1*
1*
1*
1*
1*
Description
configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6.2 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the
PCA9554/PCA9554A in a reset condition until V
DD
has reached V
POR
. At that point, the
reset condition is released and the PCA9554/PCA9554A registers and state machine will
initialize to their default states. Thereafter, V
DD
must be lowered below 0.2 V to reset the
device.
For a power reset cycle, V
DD
must be lowered below 0.2 V and then restored to the
operating voltage.
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
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