NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no
external signal externally applied because of the internal pull-up resistors.
Table 4.
Bit
7
6
5
4
3
2
1
0
I7
I6
I5
I4
I3
I2
I1
I0
Register 0 - Input Port register bit description
Symbol
Access
read only
read only
read only
read only
read only
read only
read only
read only
Value
X
X
X
X
X
X
X
X
Description
determined by externally applied logic level
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection,
not
the actual pin
value.
Table 5.
Register 1 - Output Port register bit description
Legend: * default value.
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Access
R
R
R
R
R
R
R
R
Value
1*
1*
1*
1*
1*
1*
1*
1*
Description
reflects outgoing logic levels of pins defined as
outputs by Register 3
PCA9554_9554A_7
© NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 07 — 13 November 2006
7 of 30
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