NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Name
Bit number
R/W
Default Description
SW2
6
R
0x00
Sets the operating output voltage range for SW2. Set during
OTP or TBB configuration only. See Table 53 for all possible
configurations.
UNUSED
7
—
0x00
unused
Table 56.ꢀRegister SW2STBY - ADDR 0x36
Name
Bit number
R/W
Default Description
SW2STBY
5:0
R/W
0x00
Sets the SW2 output voltage during standby mode. See
Table 53 for all possible configurations.
SW2STBY
UNUSED
6
7
R
0x00
Sets the operating output voltage range for SW2 in standby
mode. This bit inherits the value configured on bit SW2[6]
during OTP or TBB configuration. See Table 53 for all
possible configurations.
—
0x00
unused
Table 57.ꢀRegister SW2OFF - ADDR 0x37
Name
Bit number
R/W
Default Description
SW2OFF
5:0
R/W
0x00
Sets the SW2 output voltage during sleep mode. See
Table 53 for all possible configurations.
SW2OFF
UNUSED
6
7
R
0x00
Sets the operating output voltage range for SW2 in sleep
mode. This bit inherits the value configured on bit SW2[6]
during OTP or TBB configuration. See Table 53 for all
possible configurations.
—
0x00
unused
Table 58.ꢀRegister SW2MODE - ADDR 0x38
Name
Bit number
R/W
Default Description
SW2MODE
3:0
R/W
0x08
Sets the SW2 switching operation mode. See Table 29 for all
possible configurations.
UNUSED
4
5
—
0x00
0x00
unused
SW2OMODE
R/W
Set status of SW2 when in sleep mode
• 0 = OFF
• 1 = PFM
UNUSED
7:6
—
0x00
unused
Table 59.ꢀRegister SW2CONF - ADDR 0x39
Name
Bit number
R/W
Default Description
0x00
SW2 current limit level selection [1]
SW2ILIM
0
R/W
• 0 = High-level current limit
• 1 = Low-level current limit
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
57 / 137
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