LPC546xx
NXP Semiconductors
11.16 SPIFI
32-bit ARM Cortex-M4 microcontroller
The actual SPIFI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPIFI mode is
100 Mbit/s.
Table 44. Dynamic characteristics: SPIFI[1]
Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW set to
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Maximum SPIFI clock = 100
MHZ
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPIFI 1.71 V VDD 2.7 V
tDS
data set-up time
data hold time
CCLK 100 MHz
4
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz 4
-
tDH
CCLK 100 MHz
6.4
-
100 MHz < CCLK 180 MHz 6.6
-
tv(Q)
data output valid time
CCLK 100 MHz
5.7
13.7
13.7
100 MHz < CCLK 180 MHz 5.7
SPIFI 2.7 V VDD 3.6 V
tDS
data set-up time
CCLK 100 MHz
4
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz 4
-
tDH
data hold time
CCLK 100 MHz
3.5
-
100 MHz < CCLK 180 MHz 3.6
-
tv(Q)
data output valid time
CCLK 100 MHz
3.3
11.5
11.5
100 MHz < CCLK 180 MHz 3.3
[1] Based on simulation; not tested in production.
T
cy(clk)
SPIFI_SCK
t
t
h(Q)
v(Q)
DATA VALID
DATA VALID
SPIFI data out
SPIFI data in
t
t
DH
DS
DATA VALID
DATA VALID
002aah409
In mode 0, MODE3 bit (23) in SPIFI CTRL register is set to '0' (default). The SPIFI drives SCK low
after the rising edge at which the last bit of each command is captured, and keeps it LOW while CS
is HIGH.
Fig 33. SPIFI control register (Mode 0)
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
127 of 169
NXP [ NXP ]
