LPC546xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.19 USART interface
The actual USART bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for USART
master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART
slave synchronous mode is 12.5 Mbit/s.
Table 47. USART dynamic characteristics[1]
Tamb = 40 C to 105 C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
USART master (in synchronous mode) 1.71 V VDD 2.7 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK 100 MHz
21.2
19.7
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz
CCLK 100 MHz
-
-
100 MHz < CCLK 180 MHz
CCLK 100 MHz
0
-
0
4.9
4.5
100 MHz < CCLK 180 MHz
0
USART slave (in synchronous mode)1.71 V VDD 2.7 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK 100 MHz
1.7
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz
CCLK 100 MHz
1.5
-
1.2
-
100 MHz < CCLK 180 MHz
CCLK 100 MHz
1.4
-
20.2
19.3
39.5
37.7
100 MHz < CCLK 180 MHz
USART master (in synchronous mode) 2.7 V VDD 3.6 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK 100 MHz
20.5
18.9
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz
CCLK 100 MHz
-
-
100 MHz < CCLK 180 MHz
CCLK 100 MHz
0
-
1.5
1.3
3.6
3.2
100 MHz < CCLK 180 MHz
USART slave (in synchronous mode) 2.7 V VDD 3.6 V
tsu(D)
th(D)
tv(Q)
data input set-up time
data input hold time
data output valid time
CCLK 100 MHz
1.2
1
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
100 MHz < CCLK 180 MHz
CCLK 100 MHz
-
0
-
100 MHz < CCLK 180 MHz
CCLK 100 MHz
0
-
15.2
14.3
26.1
24.2
100 MHz < CCLK 180 MHz
[1] Based on characterization; not tested in production.
LPC546xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.5 — 20 June 2018
130 of 169
NXP [ NXP ]
