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LPC54616J512BD100 参数 Datasheet PDF下载

LPC54616J512BD100图片预览
型号: LPC54616J512BD100
PDF下载: 下载PDF文件 查看货源
内容描述: [32-bit ARM Cortex-M4 microcontroller]
分类和应用:
文件页数/大小: 169 页 / 3528 K
品牌: NXP [ NXP ]
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LPC546xx  
NXP Semiconductors  
32-bit ARM Cortex-M4 microcontroller  
11.15 SPI interfaces  
The actual SPI bit rate depends on the delays introduced by the external trace, the  
external device, system clock (CCLK), and capacitive loading. Excluding delays  
introduced by external device and PCB, the maximum supported bit rate for SPI master  
mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.  
Table 43. SPI dynamic characteristics[1]  
Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =  
standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
SPI master 1.71 V VDD 2.7 V  
tDS  
data set-up time  
CCLK 100 MHz  
2.2  
1.9  
6.3  
6.7  
2.6  
0.3  
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
100 MHz < CCLK 180 MHz  
CCLK 100 MHz  
-
tDH  
data hold time  
-
100 MHz < CCLK 180 MHz  
-
tv(Q)  
data output valid time CCLK 100 MHz  
5.0  
4.7  
100 MHz < CCLK 180 MHz  
SPI slave 1.71 V VDD 2.7 V  
tDS  
data set-up time  
CCLK 100 MHz  
1.1  
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
100 MHz < CCLK 180 MHz  
CCLK 100 MHz  
0.9  
-
tDH  
data hold time  
2.1  
-
100 MHz < CCLK 180 MHz  
2.2  
-
tv(Q)  
data output valid time CCLK 100 MHz  
18.8  
18.0  
37.0  
36.0  
100 MHz < CCLK 180 MHz  
SPI master 2.7 V VDD 3.6 V  
tDS  
data set-up time  
CCLK 100 MHz  
2.4  
2.2  
4.2  
4.5  
1.8  
1.7  
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
100 MHz < CCLK 180 MHz  
CCLK 100 MHz  
-
tDH  
data hold time  
-
100 MHz < CCLK 180 MHz  
-
tv(Q)  
data output valid time CCLK 100 MHz  
4.6  
4.0  
100 MHz < CCLK 180 MHz  
SPI slave 2.7 V VDD 3.6 V  
tDS  
data set-up time  
CCLK 100 MHz  
1.2  
1.0  
0
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
100 MHz < CCLK 180 MHz  
CCLK 100 MHz  
-
tDH  
data hold time  
-
100 MHz < CCLK 180 MHz  
0
-
tv(Q)  
data output valid time CCLK 100 MHz  
100 MHz < CCLK 180 MHz  
14  
13.3  
23.9  
22.2  
[1] Based on characterization; not tested in production.  
LPC546xx  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2018. All rights reserved.  
Product data sheet  
Rev. 2.5 — 20 June 2018  
124 of 169  
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