LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
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Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled;
Measured with Keil uVision v.5.23. Optimization level 0, optimized for time off.
12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.
36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,
and 180 MHz: FRO enabled; PLL enabled.
CoreMark A/MHz from SRAMX: SRAM0 is powered.
Fig 14. CoreMark power consumption: typical A/MHz vs. frequency (MHz) SRAMX
Table 15. Static characteristics: Power consumption in deep-sleep and deep power-down modes
Tamb = 40 C to +105 C, unless otherwise specified, 1.71 V VDD 2.2 V.
Symbol Parameter
IDD supply current Deep-sleep mode:
SRAMX (64KB) powered
Conditions
Min Typ[1][2] Max[3] Unit
-
-
54
-
175
A
A
Tamb = 25 C
SRAMX (64 KB) powered
2092
Tamb = 105 C
Deep power-down mode
RTC oscillator input grounded (RTC oscillator
disabled)
-
-
-
709
-
1.1
27
-
A
A
nA
Tamb = 25 C
RTC oscillator input grounded (RTC oscillator
disabled)
Tamb = 105 C
RTC oscillator running with external crystal
VDD = VDDA = VREFP = VBAT = 1.8 V
320
[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 1.8 V.
[2] Characterized through bench measurements using typical samples.
[3] Tested in production. VDD = 1.71 V. At hot temperature and below 2.0 V, the supply current increases slightly because of reduction of
available RBB (reverse body bias) voltage.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
91 of 168
NXP [ NXP ]
