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LPC54018JBD208 参数 Datasheet PDF下载

LPC54018JBD208图片预览
型号: LPC54018JBD208
PDF下载: 下载PDF文件 查看货源
内容描述: [32-bit ARM Cortex-M4 microcontroller]
分类和应用:
文件页数/大小: 168 页 / 3551 K
品牌: NXP [ NXP ]
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LPC540xx  
NXP Semiconductors  
32-bit ARM Cortex-M4 microcontroller  
10. Static characteristics  
10.1 General operating conditions  
Table 12. General operating conditions  
Tamb = 40 C to +105 C, unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
-
Typ[1]  
Max  
180  
180  
Unit  
MHz  
MHz  
fclk  
CPU clock frequency  
CPU clock frequency  
-
-
For USB high-speed device and  
host operations  
60  
CPU clock frequency  
For USB full-speed device and host  
operations  
12  
-
180  
MHz  
VDD  
supply voltage (core  
and external rail)  
1.71  
2.7  
-
-
-
-
-
-
3.6  
3.6  
V
V
V
V
V
V
[2]  
For OTP programming only  
For USB operation only  
3.0  
3.6  
VDDA  
VBAT  
Vrefp  
analog supply voltage  
battery supply voltage  
1.71  
1.71  
2.0  
3.6  
3.6  
ADC positive reference VDDA 2 V  
VDDA  
voltage  
VDDA < 2 V  
VDDA  
-
VDDA  
V
RTC oscillator pins  
Vi(rtcx) 32.768 kHz oscillator  
on pin RTCXIN  
-0.5  
-0.5  
-
-
+3.6  
+3.6  
V
V
input voltage  
Vo(rtcx)  
32.768 kHz oscillator  
output voltage  
on pin RTCXOUT  
Vi(xtal)  
crystal input voltage  
crystal output voltage  
on pin XTALIN  
0.5  
0.5  
-
-
1.95  
1.95  
V
V
Vo(xtal)  
on pin XTALOUT  
[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.  
[2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state.  
10.2 CoreMark data  
Table 13. CoreMark score  
Tamb = 25C, VDD = 3.3V  
Parameter  
ARM Cortex-M4 in active mode  
CoreMark score CoreMark code executed from SRAMX;  
Conditions  
Typical  
Unit  
[1][3][4][5]  
[1][3][4][5]  
[2][3][4][5]  
CCLK = 12 MHz  
CCLK = 96 MHz  
CCLK = 180 MHz  
3.38  
3.38  
3.38  
(Iterations/s) / MHz  
(Iterations/s) / MHz  
(Iterations/s) / MHz  
[1] Clock source FRO. PLL disabled.  
[2] Clock source 12 MHz FRO. PLL enabled.  
[3] Characterized through bench measurements using typical samples.  
[4] Compiler settings: IAR C/C++ Compiler for Arm ver 8.22.2, optimization level 3, optimized for time on.  
[5] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered.  
LPC540xx  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2018. All rights reserved.  
Product data sheet  
Rev. 1.8 — 22 June 2018  
88 of 168  
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