LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.15.4 DMA controller
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional DMA
transfers for a single source and destination.
7.15.4.1 Features
• One channel per on-chip peripheral direction: typically one for input and one for output
for most peripherals.
• DMA operations can optionally be triggered by on- or off-chip events.
• Priority is user selectable for each channel.
• Continuous priority arbitration.
• Address cache.
• Efficient use of data bus.
• Supports single transfers up to 1,024 words.
• Address increment options allow packing and/or unpacking data.
7.16 Counter/timers
7.16.1 General-purpose 32-bit timers/external event counter
The LPC540xx includes five general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.16.1.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Up to four 32-bit captures can take a snapshot of the timer value when an input signal
transitions. A capture event may also optionally generate an interrupt. The number of
capture inputs for each timer that are actually available on device pins may vary by
device.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
– Shadow registers are added for glitch-free PWM output.
• For each timer, up to four external outputs corresponding to match registers with the
following capabilities (the number of match outputs for each timer that are actually
available on device pins may vary by device):
– Set LOW on match.
– Set HIGH on match.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
78 of 168
NXP [ NXP ]
