LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
7.14.1.2 USB0 host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the Open Host Controller Interface (OHCI) specification.
Features
• OHCI compliant.
• Two downstream ports.
7.14.2 High-speed USB Host/Device interface (USB1)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
7.14.2.1 USB1 device controller
The device controller enables 480 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory. The serial
interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
Features
• Fully compliant with USB 2.0 Specification (high speed).
• Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• While USB is in the Suspend mode, the LPC540xx can enter one of the reduced
power modes and wake up on USB activity.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.14.2.2 USB1 host controller
The host controller enables high speed data exchange with USB devices attached to the
bus. It consists of register interface and serial interface engine. The register interface
complies with the Enhanced Host Controller Interface (EHCI) specification.
Features
• EHCI compliant.
• Two downstream ports.
• Supports per-port power switching.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
70 of 168
NXP [ NXP ]
