LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.13 SPI interfaces (Flexcomm Interface 0-9)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 48 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.
Table 40. SPI dynamic characteristics[1]
Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =
standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
SPI master 1.71 V VDD 2.7 V
tDS
data set-up time
CCLK 100 MHz
CCLK > 100 MHz
CCLK 100 MHz
CCLK > 100 MHz
2.2
1.9
6.3
6.7
2.6
0.3
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
tDH
data hold time
-
-
tv(Q)
data output valid time CCLK 100 MHz
5.0
4.7
CCLK > 100 MHz
SPI slave 1.71 V VDD 2.7 V
tDS
data set-up time
CCLK 100 MHz
CCLK > 100 MHz
CCLK 100 MHz
CCLK > 100 MHz
1.1
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
0.9
-
tDH
data hold time
2.1
-
2.2
-
tv(Q)
data output valid time CCLK 100 MHz
18.8
18.0
37.0
36.0
CCLK > 100 MHz
SPI master 2.7 V VDD 3.6 V
tDS
data set-up time
CCLK 100 MHz
CCLK > 100 MHz
CCLK 100 MHz
CCLK > 100 MHz
2.4
2.2
4.2
4.5
1.8
1.7
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
tDH
data hold time
-
-
tv(Q)
data output valid time CCLK 100 MHz
4.6
4.0
CCLK > 100 MHz
SPI slave 2.7 V VDD 3.6 V
tDS
data set-up time
CCLK 100 MHz
CCLK > 100 MHz
CCLK 100 MHz
CCLK > 100 MHz
1.2
1.0
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
-
tDH
data hold time
-
0
-
tv(Q)
data output valid time CCLK 100 MHz
14
13.3
23.9
22.2
CCLK > 100 MHz
[1] Based on characterization; not tested in production.
LPC540xx
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
123 of 168
NXP [ NXP ]
