LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.14 SPI interfaces (Flexcomm Interface 10)
The actual SPI bit rate depends on the delays introduced by the external trace, the
external device, system clock (CCLK), and capacitive loading. Excluding delays
introduced by external device and PCB, the maximum supported bit rate for SPI master
mode is 50 Mbit/s, and the maximum supported bit rate for SPI slave mode is 50 Mbit/s.
Table 41. SPI dynamic characteristics[1]
Tamb = 40 C to 105 C; 1.71 V VDD 3.6 V; CL = 30 pF balanced loading on all pins; Input slew
= 1 ns, SLEW setting = standard mode for all pins;. Parameters sampled at the 50 % level of the
rising or falling edge.
Symbol Parameter
SPI master
Conditions Min
Typ
Max
Unit
tDS
data set-up time
0
-
-
-
-
ns
ns
ns
tDH
data hold time
10.0
0.8
-
tv(Q)
SPI slave
tDS
data output valid time
10.0
data set-up time
data hold time
1.2
-
-
-
-
ns
ns
ns
tDH
10.0
4.28
-
tv(Q)
data output valid time
10.0
[1] Based on characterization; not tested in production.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
126 of 168
NXP [ NXP ]
