LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 24. Dynamic characteristics: Static external memory interface …continued
CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter[1]
Conditions[1]
Min
5.5
0.7
Typ
Max
-
Unit
ns
[2][4]
[6]
th(D) data input hold time
RD6
-
-
tCSHBLSH CS HIGH to BLS HIGH PB = 1
time
1.5
ns
[2]
[2]
[2]
tCSHOEH CS HIGH to OE HIGH
time
0.5
-
-
-
0.9
0
ns
ns
ns
tOEHANV OE HIGH to address
invalid time
RD8
RD7
0.4
0.5
tdeact
deactivation time
0.9
Write cycle parameters[2]
tCSLAV
tCSLDV
CS LOW to address
valid time
WR1
0.1
1
-
-
-
0.5
2.2
ns
ns
CS LOW to data valid WR2
time
[2][6]
tCSLWEL CS LOW to WE LOW
time
WR3; PB =1
0.5 +
(WAITWEN + 1)
Tcy(clk)
(WAITWEN + 1) Tcy(clk) ns
[2][6]
[2][6]
tCSLBLSL CS LOW to BLS LOW WR4; PB = 1
time
1.9
-
-
0
ns
tWELWEH WE LOW to WE HIGH WR5; PB =1
time
0.1 +
(WAITWEN + 1)
Tcy(clk)
(WAITWEN + 1) Tcy(clk) ns
[2][6]
[2][6]
[2][5][6]
[6]
tBLSLBLSH BLS LOW to BLS
HIGH time
PB = 1
3.1
-
-
-
-
-
-
-
6.7
ns
ns
ns
ns
ns
ns
tWEHDNV WE HIGH to data
invalid time
WR6; PB =1
WR7; PB = 1
PB = 1
1.6 + Tcy(clk)
0.5+Tcy(clk)
0.8
2.8 + Tcy(clk)
tWEHEOW WE HIGH to end of
write time
0.8 + Tcy(clk)
tBLSHDNV BLS HIGH to data
invalid time
0
[6]
tWEHANV WE HIGH to address
invalid time
PB = 1
0.5
0.8
0
[2][6]
[2][6]
tdeact
deactivation time
WR8; PB = 0;
PB = 1
0.8
tCSLBLSL CS LOW to BLS LOW WR9; PB = 0
1.9
(WAITWEN + 1) Tcy(clk) ns
+ (WAITWEN + 1)
Tcy(clk)
[2][6]
tBLSLBLSH BLS LOW to BLS
HIGH time
WR10; PB = 0
WR11; PB = 0
3.1+ (WAITWR
WAITWEN + 1)
Tcy(clk)
-
6.7+ (WAITWR
WAITWEN + 1) Tcy(clk)
ns
[2][5][6]
[2][6]
tBLSHEOW BLS HIGH to end of
write time
0.8
-
-
Tcy(clk)
ns
ns
+ Tcy(clk)
0.2 + Tcy(clk)
tBLSHDNV BLS HIGH to data
invalid time
WR12;
PB = 0
0.5 + Tcy(clk)
[1] Parameters are shown as RDn or WDn in Figure 23 as indicated in the Conditions column.
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
106 of 168
NXP [ NXP ]
