LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
11.3 External memory interface
Table 23. Dynamic characteristics: Static external memory interface
CL = 10 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter[1]
Conditions[1]
Min
Typ
Max
Unit
Read cycle parameters
tCSLAV
CS LOW to address
valid time
RD1
RD2
1.2
-
-
-
-
1.6
ns
ns
ns
ns
[2]
[2][6]
[2]
tCSLOEL
CS LOW to OE LOW
time
0.4+ Tcy(clk)
WAITOEN
0.8+ Tcy(clk)
WAITOEN
tCSLBLSL CS LOW to BLS LOW RD3; PB = 1
time
1.6
0
tOELOEH OE LOW to OE HIGH RD4
time
(WAITRD
WAITOEN + 1)
Tcy(clk)
0.3
+ (WAITRD
WAITOEN + 1)
Tcy(clk)
[2][3]
tam
memory access time
RD5
6.7
-
-
ns
+ (WAITRD
WAITOEN +1)
Tcy(clk)
[2][4]
[6]
th(D)
data input hold time
RD6
4.8
-
-
-
ns
ns
tCSHBLSH CS HIGH to BLS HIGH PB = 1
time
0.8
1.5
[2]
[2]
[2]
tCSHOEH CS HIGH to OE HIGH
time
0.5
-
-
-
0.9
0
ns
ns
ns
tOEHANV OE HIGH to address
invalid time
0.4
0.5
tdeact
Write cycle parameters
tCSLAV CS LOW to address
valid time
deactivation time
RD7
0.9
WR1
0.1
-
-
-
-
-
0.5
2.2
0
ns
ns
ns
ns
ns
tCSLDV
CS LOW to data valid WR2
time
1.0
[2][6]
[2][6]
[2][6]
tCSLWEL CS LOW to WE LOW
time
WR3; PB =1
0.6
1.2
tCSLBLSL CS LOW to BLS LOW WR4; PB = 1
time
0
tWELWEH WE LOW to WE HIGH WR5; PB =1
time
(WAITWR
WAITWEN + 1)
Tcy(clk)
0.1
+ (WAITWR
WAITWEN + 1)
Tcy(clk)
[2][6]
[2][6]
tBLSLBLSH BLS LOW to BLS
HIGH time
PB = 1
2.5
1.6
0.6
-
-
-
5.5
2.9
0.9
ns
ns
ns
tWEHDNV WE HIGH to data
invalid time
WR6; PB =1
WR7; PB = 1
[2][5][6]
tWEHEOW WE HIGH to end of
write time
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
104 of 168
NXP [ NXP ]
