LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
Table 23. Dynamic characteristics: Static external memory interface …continued
CL = 10 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter[1]
Conditions[1]
Min
Typ
Max
Unit
[6]
[6]
tBLSHDNV BLS HIGH to data
invalid time
PB = 1
0.8
-
0
ns
tWEHANV WE HIGH to address
invalid time
PB = 1
0.6
-
-
-
0.9
0
ns
ns
[2][6]
[2][6]
tdeact
deactivation time
WR8; PB = 0;
PB = 1
0.8
1.2
tCSLBLSL CS LOW to BLS LOW WR9; PB = 0
(WAITWEN + 1) ns
Tcy(clk)
+ (WAITWEN + 1)
Tcy(clk)
[2][6]
tBLSLBLSH BLS LOW to BLS
HIGH time
WR10; PB = 0
2.5
-
5.5
ns
+ (WAITWR
WAITWEN + 1)
Tcy(clk)
+ (WAITWR
WAITWEN + 1)
Tcy(clk)
[2][5][6]
[2][6]
tBLSHEOW BLS HIGH to end of
write time
WR11; PB = 0
0.8
-
-
Tcy(clk)
ns
ns
+ Tcy(clk)
0.2 + Tcy(clk)
tBLSHDNV BLS HIGH to data
invalid time
WR12;
PB = 0
0.5 + Tcy(clk)
[1] Parameters are shown as RDn or WDn in Figure 23 as indicated in the Conditions column.
[2] Tcy(clk) = 1/EMC_CLK (see UM11060 LPC540xx manual).
[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).
[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.
[5] End Of Write (EOW): Earliest of address invalid, EMC_CSx HIGH, EMC_BLSx HIGH (PB = 1).
[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM11060
LPC540xx manual).
Table 24. Dynamic characteristics: Static external memory interface
CL = 20 pF balanced loading on all pins, Tamb = 40 C to 105 C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input
slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding
delays introduced by external device and PCB; Values based on simulation.
Symbol Parameter[1]
Conditions[1]
Min
Typ
Max
Unit
Read cycle parameters
tCSLAV
CS LOW to address
valid time
RD1
RD2
1.2
-
-
-
-
1.6
ns
[2]
[2][6]
[2]
tCSLOEL
CS LOW to OE LOW
time
0.5+ Tcy(clk)
WAITOEN
0.8+ Tcy(clk) WAITOEN ns
tCSLBLSL CS LOW to BLS LOW RD3; PB = 1
time
2.3
0
ns
ns
tOELOEH OE LOW to OE HIGH RD4
time
(WAITRD
WAITOEN + 1)
Tcy(clk)
0.3
+ (WAITRD
WAITOEN + 1) Tcy(clk)
[2][3]
tam
memory access time
RD5
7.9
-
-
ns
+ (WAITRD
WAITOEN +1)
Tcy(clk)
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
105 of 168
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