NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
14
13
14
CP1
CP0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
15
MR
Q7
Q8
Q9
Q5-9
001aah239
CTRDIV10/DEC
&
CT = 0
0
1
2
3
4
5
6
7
8
9
CT≥5
001aah240
3
2
4
7
10
1
5
6
9
11
12
3
2
4
7
10
1
5
6
9
11
12
13
15
Fig 3.
Logic symbol
Fig 4.
IEE logic symbol
6. Pinning information
6.1 Pinning
HEF4017B
Q5
Q1
Q0
Q2
Q6
Q7
Q3
V
SS
1
2
3
4
5
6
7
8
001aae574
16 V
DD
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
9
Q8
Fig 5.
Pin configuration
6.2 Pin description
Table 2.
Symbol
Q0 to Q9
V
SS
Q5-9
CP1
Pin description
Pin
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
8
12
13
Description
decoded output
ground supply voltage
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
HEF4017B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 9 December 2008
3 of 16
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