NXP Semiconductors
HEF4049B
Hex inverting buffers
V
DD
V
I
G
RT
V
O
DUT
CL
001aag182
Test data is given in
Definitions for test circuit:
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
Fig 6.
Table 10.
Load circuitry for switching times
Test data
Input
V
I
V
M
0.5V
I
t
r
, t
f
≤
20 ns
V
DD
Load
C
L
50 pF
Supply voltage
5 V to 15 V
HEF4049B_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
6 of 11