NXP Semiconductors
HEF4049B
Hex inverting buffers
5. Functional diagram
1A
3
2
1Y
2A
5
4
2Y
3A
7
6
3Y
4A
9
10
4Y
5A
11
12
5Y
input
6Y
A
Y
mna341
6A
14
15
V
SS
001aae604
001aai331
Fig 1.
Logic symbol
Fig 2.
Logic diagram for one gate
Fig 3.
Input protection circuit
6. Pinning information
6.1 Pinning
HEF4049B
V
DD
1Y
1A
2Y
2A
3Y
3A
V
SS
1
2
3
4
5
6
7
8
001aae602
16 n.c.
15 6Y
14 6A
13 n.c.
12 5Y
11 5A
10 4Y
9
4A
Fig 4.
Pin configuration
6.2 Pin description
Table 2.
Symbol
V
DD
1Y to 6Y
Pin description
Pin
1
2, 4, 6, 10, 12, 15
Description
supply voltage
output
HEF4049B_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 11 November 2008
2 of 11
PHILIPS [ NXP SEMICONDUCTORS ]
