FXPS7115DS4 参数 Datasheet PDF下载

型号：	FXPS7115DS4
PDF下载：	下载PDF文件查看货源
内容描述：	[Digital absolute pressure sensor, 40 kPa to 115 kPa]
分类和应用：	传感器换能器
文件页数/大小：	72 页 / 1041 K
品牌：	NXP [ NXP ]

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Symbol

Parameter

Condition

Min

Typ

Max

Units

[1]

t_{SCLH_100}

t_{SCLH_400}

t_{SCLH_1000}

Clock (SCL) high time

100 kHz mode

400 kHz mode

—

4.00

0.60

0.50

—

μs

(70 % of V_CCto 70 % of V_CC

)

1000 kHz mode (not

compliant with UM10204,

rev.6)

[1]

t_{SCLL_100}

t_{SCLL_400}

t_{SCLL_1000}

Clock (SCL) low time

100 kHz mode

400 kHz mode

1000 kHz mode

—

4.70

1.30

0.50

—

μs

(30 % of V_CCto 30 % of V_CC

)

[1]

t_{SRISE_100}

t_{SRISE_400}

t_{SRISE_1000}

Clock (SCL) and data (SDA) rise time

(30 % of V_CCto 70 % of V_CC

100 kHz mode

400 kHz mode

1000 kHz mode

—

1000

300

)

120

[1]

t_{SFALL_100}

t_{SFALL_400}

t_{SFALL_1000}

Clock (SCL) and data (SDA) fall time

—

300

120

100 kHz mode

400 kHz mode

1000 kHz mode

(70 % of V_CCto 30 % of V_CC

)

[1]

t_{SETUP_100}

t_{SETUP_400}

t_{SETUP_1000}

Data input setup time

100 kHz mode

—

250

100

—

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{HOLD_100}

t_{HOLD_400}

t_{HOLD_1000}

Data input hold time

100 kHz mode

—

900

300

(SCL = 70 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STARTSETUP_100}

t_{STARTSETUP_400}

t_{STARTSETUP_1000}

Start condition setup time

100 kHz mode

—

4.70

0.60

0.26

—

μs

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STARTHOLD_100}

t_{STARTHOLD_400}

t_{STARTHOLD_1000}

Start condition hold time

100 kHz mode

—

4.00

0.60

0.26

—

μs

(SCL = 70 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STOPSETUP_100}

t_{STOPSETUP_400}

t_{STOPSETUP_1000}

Stop condition setup time

100 kHz mode

—

4.00

0.60

0.26

—

μs

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{VALID_100}

t_{VALID_400}

t_{VALID_1000}

SCLK low to data valid

100 kHz mode

—

3.45

0.90

0.45

μs

(SCL = 30 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{FREE_100}

t_{FREE_400}

t_{FREE_1000}

Bus free time

100 kHz mode

—

4.00

1.30

0.50

—

μs

(SDA = 70 % of V_CCto SDA = 70 % of 400 kHz mode

V_CC

)

1000 kHz mode

[2]

C_BUS

SPI

Bus capacitive load

—

400

[1]

t_SCLK

Serial interface timing^[3]

Clock (SCLK) period (10 %

—

of V_CCto 10 % of V_CC

)

t_SCLKH

t_SCLKL

t_SCLKR

t_SCLKF

t_LEAD

Clock (SCLK) period (90 %

of V_CCto 90 % of V_CC

)

Clock (SCLK) period (10 %

of V_CCto 10 % of V_CC

)

Serial interface timing^[3]

Clock (SCLK) period (10 %

of V_CCto 90 % of V_CC

)

Clock (SCLK) period (90 %

of V_CCto 10 % of V_CC

)

Serial interface timing^[3]

SS_B asserted to SCLK

high (SS_B = 10 % of V_CC

to SCLK = 10 % of V_CC

)

[1]

t_ACCESS

SS_B asserted to SCLK

high (SS_B = 10 % of V_CC

to MISO = 10/90 % of V_CC

—

)

t_SETUP

SS_B asserted to SCLK

high (MOSI = 10/90 % of

V_CCto SCLK = 10 % of

V_CC

)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

57 / 72

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