NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Symbol
Parameter
Condition
Min
Typ
Max
Units
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
tHOLD_IN
Serial interface timing[3]
MOSI data hold time
(SCLK = 90 % of VCC to
MOSI = 10/90 % of VCC
—
10
—
ns
)
tHOLD_OUT
MOSI data hold time
(SCLK = 90 % of VCC to
MISO = 10/90 % of VCC
0
—
—
30
—
60
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
)
tVALID
Serial interface timing[3]
Serial interface timing[3]
Serial interface timing[3]
Serial interface timing[3]
Serial interface timing[3]
Serial interface timing[3]
SCLK low to data valid
(SCLK = 10 % of VCC to
MISO = 10/90 % of VCC
—
—
—
—
—
—
—
—
)
tLAG
SCLK low to SS_B high
(SCLK = 10 % of VCC to
60
—
SS_B = 90 % of VCC
)
tDISABLE
SS_B high to MISO disable
(SS_B = 90 % of VCC to
MISO = Hi Z)
tSSN
SS_B high to SS_B low
(SS_B = 90 % of VCC to
500
50
50
—
SS_B = 90 % of VCC
)
tSLKSS
SCLK low to SS_B low
(SCLK = 10 % of VCC to
SS_B = 90 % of VCC
)
tSSCLK
SS_B high to SCLK high
(SS_B = 90 % of VCC to
SCLK = 90 % of VCC
)
tLAT_SPI
Signal chain
tSigChain
fc0
Data latency
[4]
PABS low-pass filter
Signal chain sample time
—
—
48
—
—
μs
[2] [4]
Cutoff frequency, filter
option #0, 4-pole
800
Hz
[2] [4]
[4]
fc1
Cutoff frequency, filter
option #1, 4-pole
—
1000
—
—
Hz
μs
tSigDelay
Signal delay (sinc filter to output delay,
excluding the PABS LPF)
—
128
—
[4]
fPackage
Package resonance frequency
27.1
—
kHz
Supply and support circuitry
[2]
tVCC_POR
Reset recovery (all modes, excluding
VCC voltage ramp time)
VCC = VCCMIN to POR
release
—
—
1
ms
[4]
[4]
[2]
tPOR_I2C/POR_SPI
tPOR_DataValid
POR to first SPI command
POR to sensor data valid
0.400
—
—
—
—
0.700
ms
ms
ms
6
6
tRANGE_DataValid
DSP setting change to
sensor data valid
—
[4]
[4]
tSOFT_RESET_I2C
Soft reset activation time, command
complete to reset (no ACK follows)
—
—
—
—
700
700
ns
ns
tSOFT_RESET_SPI
Soft reset activation time, SS_B high to
reset
[4]
[4]
tCC_POR
VCC undervoltage detection delay
—
—
—
5
μs
μs
tUVOV_RCV
Undervoltage/overvoltage recovery
delay
100
—
[1] Parameter verified by characterization.
[2] Parameter verified by functional evaluation.
[3] See Section 7.5.6, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ
[4] Functionality verified by modeling, simulation and/or design verification.
FXPS7115D4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
58 / 72
NXP [ NXP ]
