NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
6.2 Pin description
Table 3.ꢀPin description
Pin
Pin name
Description
3
INT
Interrupt output
The output can be configured to be active low or active high. If unused, NXP
recommends pin 3 be unterminated. Optionally, pin 3 can be tied to VSS
.
1, 16
VCC
Power supply
Supply return (ground)
Test pin
4, 15
VSS
2, 5, 12
TESTx
NXP recommends pins 2, 5, and 12 be unterminated. Optionally, these pins can
be tied to VSS
6, 7, 14
8
NC
No connect
SS_B
Slave / Device select
In I2C mode, input pin 8 must be connected to VCC with an external pull-up
resistor, as shown in the application diagram.
In SPI mode, input pin 8 provides the slave select for the SPI port. An internal
pull-up device is connected to this pin.
9
SCLK/SCL
In I2C mode, input pin 9 provides the serial clock. This pin must be connected to
VCC with an external pull-up resistor, as shown in the application diagram.
In SPI mode, input pin 9 provides the serial clock. An internal pull-down device is
connected to this pin.
10
11
MOSI
SPI data in
In SPI mode, pin 10 functions as the serial data input to the SPI port. An internal
pull-down device is connected to this pin.
MISO/SDA
SPI/I2C data out
In I2C mode, pin 11 functions as the serial data input/output. Pin 11 must be
connected to VCC with an external pull-up resistor, as shown in the application
diagram.
In SPI mode, pin 11 functions as the serial data output.
13
17
VCCIO
PAD
I/O supply
Pin 13 must be connected to VCC, the device supply.
Die attach pad
Pin 17 is the die attach flag, and must be connected to VSS
.
7 Functional description
7.1 Voltage regulators
The device derives its internal supply voltage from the VCC and VSS pins. An external
filter capacitor is required for VCC, as shown in Figure 25 and Figure 26.
A reference generator provides a reference voltage for the ΣΔ converter.
FXPS7115D4
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
4 / 72
NXP [ NXP ]
