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FXPS7115DS4 参数 Datasheet PDF下载

FXPS7115DS4图片预览
型号: FXPS7115DS4
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital absolute pressure sensor, 40 kPa to 115 kPa]
分类和应用: 传感器换能器
文件页数/大小: 72 页 / 1041 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXPS7115D4  
Digital absolute pressure sensor, 40 kPa to 115 kPa  
Table 29.ꢀSPI Response Message CRC  
SPICRCSEED[3:0]  
Default Polynomial  
x8+ x5+ x3+ x2+ x + 1  
x8+ x5+ x3+ x2+ x + 1  
Default non-direct Seed  
1111 1111  
0000  
nonzero  
1111 SPICRCSEED[3:0]  
7.5.5 Exception handling  
7.5.5.1 Basic status field  
All responses include a status field (ST[1:0]) that includes the general status of the  
device and transmitted data as described below. The contents of the status field is  
a representation of the device status at the rising edge of SS_B for the previous SPI  
command.  
Table 30.ꢀBasic status field for responses to register commands  
ST[1:0]  
Status  
Description  
SF[1:0]  
Priority  
0
0
Device in Initialization  
Device in initialization (ENDINIT not  
set)  
0
0
3
0
1
1
0
Normal Mode  
Self-test  
Normal mode(ENDINIT set)  
0
0
0
0
4
2
Self-test(ST_CTRL[3:0] not equal to  
'0000')  
1
1
Internal Error Present  
Detailed Status Field  
Detailed  
1
Status Field  
7.5.5.2 Error responses  
Table 31.ꢀError responses bit field descriptions  
SF[1:0]  
Status Sources  
DEVSTAT State  
Bit set in DEVSTAT3  
0
0
Oscillator training error (OSCTRAIN_ERR)  
Offset error (PABS_HIGH or PABS_LOW or CM_ Bit set in DSP_STAT  
ERROR)  
Bit set in DEVSTAT2  
Temperature error  
0
1
1
1
0
1
User OTP memory error (UF2 or UF1)  
User R/W memory error (UF2)  
NXP OTP Memory error  
U_OTP_ERR set in DEVSTAT2  
U_RW_ERR set in DEVSTAT2  
F_OTP_ERR set in DEVSTAT2  
Test Mode active  
Supply error  
TESTMODE bit set in DEVSTAT  
bit set in DEVSTAT1  
DEVRES set  
Reset error  
MISO error  
SPI error  
Bit set in DEVSTAT3  
N/A  
7.5.5.3 SPI error  
The following external SPI conditions result in a SPI error:  
SCLK is high when SS_B is asserted  
The number of SCLK rising edges detected while SS_B is asserted is not equal to 16  
SCLK is high when SS_B is deasserted  
CRC error is detected (MOSI)  
A register write command to any register other than the DEVLOCK_WR register is  
received while ENDINIT is set  
If a SPI error is detected, the device responds with the error response as described  
in Section 7.5.5.2 "Error responses" with the detailed status field set to “SPI Error” as  
defined in Section 7.5.5.1 "Basic status field".  
FXPS7115D4  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Product data sheet  
Rev. 3 — 5 December 2019  
26 / 72  
 
 
 
 
 
 
 
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