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FXPS7115DS4 参数 Datasheet PDF下载

FXPS7115DS4图片预览
型号: FXPS7115DS4
PDF下载: 下载PDF文件 查看货源
内容描述: [Digital absolute pressure sensor, 40 kPa to 115 kPa]
分类和应用: 传感器换能器
文件页数/大小: 72 页 / 1041 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXPS7115D4  
Digital absolute pressure sensor, 40 kPa to 115 kPa  
7.5.5.4 SPI data output verification error  
The device includes a function to verify the integrity of the data output to the MISO pin.  
The function compares the data transmitted on the MISO pin to the data intended to be  
transmitted. If any one bit does not match, a SPI MISO mismatch fault is detected and  
the MISO_ERR flag in the DEVSTAT2 register is set.  
If a valid sensor data request message is received during the SPI transfer with the MISO  
mismatch failure, the request is ignored and the device responds with the error response  
as described in Section 7.5.5.2 "Error responses" with the detailed status field set to  
“SPI Error” as defined in Section 7.5.5.1 "Basic status field" during the subsequent SPI  
message.  
If a valid register write request message is received during the SPI transfer with the  
MISO mismatch failure, the register write is completed as requested, but the device  
responds with the error response as described in Section 7.5.5.2 "Error responses" with  
the detailed status field set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field"  
during the subsequent SPI message.  
If a valid register read request message is received during the SPI transfer with the MISO  
mismatch failure, the register read is ignored and the device responds with the error  
response as described in Section 7.5.5.2 "Error responses" with the detailed status field  
set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field", during the subsequent  
SPI message.  
SPI DATA OUT SHIFT REGISTER  
DATA OUT BUFFER  
MISO  
D
Q
D
Q
R
MISO ERR  
D
Q
SCLK  
R
aaa-023748  
Figure 21.ꢀSPI data output verification  
7.5.6 SPI timing diagram  
DSP Out  
t
LAT  
SS_B  
t
t
t
t
SSN  
LEAD  
SCLKR  
SCLKF  
t
t
SSCLK  
t
SCLKH  
SCLK  
SCLK  
t
t
t
CLKSS  
SCLKL  
LAG  
t
ACCESS  
t
t
HOLD_OUT  
t
VALID  
DISABLE  
MISO  
t
HOLD_IN  
t
SETUP  
MOSI  
aaa-023749  
Figure 22.ꢀSPI timing diagram  
FXPS7115D4  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Product data sheet  
Rev. 3 — 5 December 2019  
27 / 72  
 
 
 
 
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