NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
Table 27.ꢀReserved command response message bit field descriptions
Bit field
Definition
Command echo
Data
Reserved command echo. Undefined
Response data. Undefined
8-bit CRC
CRC[7:0]
7.5.4 Error checking
7.5.4.1 Default 8-bit CRC
7.5.4.1.1 Command error checking
The device calculates an 8-bit CRC on the entire 32 bits of each command. Message
data is entered into the CRC calculator MSB first, consistent with the transmission
order of the message. If the calculated CRC does not match the transmitted CRC, the
command is ignored and the device responds with the SPI error response.
The CRC decoding procedure is as follows:
1. A seed value is preset into the LSB of the shift register.
2. Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the LSB of the shift register in the order received (MSB first).
3. When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
4. If the shift register contains all zeros, the CRC is correct.
5. If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 28.
Table 28.ꢀSPI Command Message CRC
SPICRCSEED[3:0]
Default Polynomial
x8+ x5+ x3+ x2+ x + 1
x8+ x5+ x3+ x2+ x + 1
Default non-direct Seed
1111 1111
0000
non-zero
1111 SPICRCSEED[3:0]
7.5.4.1.2 Response error checking
The device calculates a CRC on the entire 32 bits of each response. Message data is
entered into the CRC calculator MSB first, consistent with the transmission order of the
message.
The CRC encoding procedure is as follows:
1. A seed value is preset into the LSB of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message and CRC into the LSB of the shift register (MSB first).
3. Following the transmitted message, the transmitter feeds 8 zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed are shown in Table 29.
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
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