NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
7.4.7 I2C timing diagram
t
f
t
r
t
SU;DAT
70 %
30 %
70 %
30 %
SDA
SCL
... cont.
t
VD;DAT
t
t
t
r
HD;DAT
f
t
HIGH
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
... cont.
th
9
clock
t
t
HD;STA
1 / f
1
LOW
SCL
clock cycle
S
st
t
BUF
... SDA
... SCL
t
SU;STA
t
VD;ACK
t
t
SU;STO
t
SP
HD;STA
70 %
30 %
Sr
P
S
th
9
clock
aaa-029751
Figure 19.ꢀI2C timing diagram
7.5 Standard 32-bit SPI protocol
The device includes a standard SPI protocol requiring 32-bit data packets. The device
is a slave device and requires that the base clock value be low (CPOL = 0) with data
captured on the rising edge of the clock and data propagated on the falling edge of the
clock (CPHA = 0). The most significant bit is transferred first (MSB first). SPI transfers are
completed through a sequence of two phases. During the first phase, the command is
transmitted from the SPI master to the device. During the second phase, response data
is transmitted from the slave device. MOSI and SCLK transitions are ignored when SS_B
is not asserted.
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
18 / 72
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