NXP Semiconductors
FXPS7115D4
Digital absolute pressure sensor, 40 kPa to 115 kPa
7.4.1 I2C bit transmissions
The state of SDA when SCL is high determines the bit value being transmitted. SDA
must be stable when SCL is high and change when SCL is low as shown in Figure 14.
After the START signal has been transmitted by the master, the bus is considered busy.
Timing for the start condition is specified in Table 102.
SDA
SCL
SDA stable
SDA = `1'
SDA stable
SDA = `0'
SDA
changes
aaa-029746
Figure 14.ꢀI2C bit transmissions
7.4.2 I2C start condition
A bus operation is always started with a start condition (START) from the master.
A START is defined as a high to low transition on SDA while SCL is high as shown
in Figure 15. After the START signal has been transmitted by the master, the bus is
considered busy. Timing for the start condition is specified in Table 102.
A start condition (START) and a repeat START condition (rSTART) are identical.
SDA
SCL
START
aaa-029747
Figure 15.ꢀI2C start condition
7.4.3 I2C byte transmission
Data transfers are completed in byte increments. The number of bytes that can be
transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge
bit (Section 7.4.4 "I2C acknowledge and not acknowledge transmissions") from the
receiver. Data is transferred with the most significant bit (MSB) first (see Figure 16).
The master generates all clock pulses, including the ninth clock for the acknowledge bit.
Timing for the byte transmissions is specified in Section 7.4.4 "I2C acknowledge and
not acknowledge transmissions". All functions for this device are completed within the
acknowledge clock pulse. Clock stretching is not used.
FXPS7115D4
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© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 3 — 5 December 2019
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