NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
changes direction at the transition from the value set in the modulus register and the next
lower count value. This corresponds to the end of a PWM period. (The 0x0000 count
value corresponds to the center of a period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built
into the timer counter for read operations. Whenever either byte of the counter is read
(TPM1CNTH or TPM1CNTL), both bytes are captured into a buffer so when the other
byte is read, the value will represent the other byte of the count at the time the first byte
was read. The counter continues to count normally, but no new value can be read from
either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either
byte of the timer count TPM1CNTH or TPM1CNTL. Resetting the counter in this manner
also resets the coherency mechanism in case only one byte of the counter was read
before resetting the count.
11.5.2 Channel mode selection
Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and
MSnA control bits in the channel n status and control registers determine the basic
mode of operation for the corresponding channel. Choices include input capture, output
compare, and buffered edge-aligned PWM.
11.5.2.1 Input capture mode
With the input capture function, the TPM1 can capture the time at which an external
event occurs. When an active edge occurs on the pin of an input capture channel,
the TPM1 latches the contents of the TPM1 counter into the channel value registers
(TPM1CnVH:TPM1CnVL). Rising edges, falling edges, or any edge may be chosen as
the active edge that triggers an input capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a
buffer to support coherent 16-bit accesses regardless of order. The coherency sequence
can be manually reset by writing to the channel status/control register (TPM1CnSC).
An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt
request.
11.5.2.2 Output compare mode
With the output compare function, the TPM1 can generate timed pulses with
programmable position, polarity, duration, and frequency. When the counter reaches the
value in the channel value registers of an output compare channel, the TPM1 can set,
clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel
value registers only after both 8-bit bytes of a 16-bit register have been written. This
coherency sequence can be manually reset by writing to the channel status/control
register (TPM1CnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU
interrupt request.
11.5.2.3 Edge-aligned PWM mode
This type of PWM output uses the normal up-counting mode of the timer counter
(CPWMS = 0) and can be used when other channels in the same TPM1 are configured
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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