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F87EHHD 参数 Datasheet PDF下载

F87EHHD图片预览
型号: F87EHHD
PDF下载: 下载PDF文件 查看货源
内容描述: [FXTH87E, Family of Tire Pressure Monitor Sensors]
分类和应用:
文件页数/大小: 183 页 / 1700 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXTH87E  
FXTH87E, Family of Tire Pressure Monitor Sensors  
period of the resulting interrupt also generates the clock, RCLK, for the periodic reset  
timing.  
Table 99.ꢀPWU Control/Status register 0 (PWUCS0) (address $0039)  
Bit  
R
7
WUF  
0
6
0
5
4
3
2
1
0
WUT[5:0]  
W
WUFAK  
Reset  
1
1
1
1
1
1
Table 100.ꢀPWUSC0 register field descriptions  
Field  
Description  
Wakeup Interrupt Flag — The WUF bit indicates when a wakeup interrupt has been generated by the PWU.  
This bit is cleared  
7
by writing a one to the WUFAK bit. Writing a zero to this bit has no effect. Reset clears this bit.  
0ꢀWakeup interrupt not generated or was previously acknowledged.  
1ꢀWakeup interrupt generated.  
WUF  
Acknowledge WUF Interrupt Flag — The WUFAK bit clears the WUF bit if written with a one. Writing a zero  
to the WUFAK bit has no effect on the WUF bit. Reading the WUFAK bit returns a zero. Reset has no effect  
on this bit.  
6
WUFAK  
0ꢀNo effect.  
1ꢀClear WUF bit.  
WUF Time Interval — These control bits select the number of WCLK clocks that are needed before the next  
wakeup interrupt is generated. The count gives a range of wakeup times from 1 to 63 WCLK clocks.  
Depending on the value of the bits for the WDIV[5:0] this time interval can nominally be from 1 to 63  
seconds in 1 second steps.  
Whenever the WUT[5:0] bits are changed the timeout period is restarted. Writing the same data to the  
WUT[5:0] bits has no effect.  
5:0  
WUT[5:0]  
Writing zeros to all of the WUT[5:0] bits forces the wakeup divider to a value of $3F and disables the  
wakeup interrupt. However,  
writing all zeros to the WUT[5:0] bits is inhibited if all of the PRST[5:0] bits are already cleared to zero. This  
prevents disabling both the periodic wakeup and the periodic reset at the same time. See Table 101.  
The WUT[5:0] bits are preset to a value of $3F (decimal 63) by any resets.  
Table 101.ꢀLimitations on clearing WUT/PRST  
Resulting  
Wakeup  
Interrupt  
State of Control Control Bits to Resulting  
Resulting  
Periodic Reset  
Control Bits  
Bits  
be Cleared  
Action  
non-zero  
all zero  
Allowed  
Inhibited  
Allowed  
Inhibited  
Enabled [1]  
Disabled [2]  
Disabled  
Disabled  
Enabled[1]  
Enabled[1]  
Disabled  
WUT[5:0]  
PRST[5:0]  
PRST[5:0]  
non-zero  
all zero  
WUT[5:0]  
Enabled[1]  
[1] Using previous values.  
[2] Wakeup divider preset to $3F.  
FXTH87ERM  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Reference manual  
Rev. 5.0 — 4 February 2019  
109 / 183  
 
 
 
 
 
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