NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 4.
Input
nSD
H
H
[1]
Function table
Output
nRD
H
H
nCP
↑
↑
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level
L = LOW voltage level
↑
= LOW-to-HIGH transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
X = don’t care
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
Min
−0.5
−50
−0.5
-
Max
+6.5
-
+6.5
±50
V
CC
+ 0.5
±50
100
-
+150
500
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
−0.5
-
-
−100
−65
T
amb
=
−40 °C
to +125
°C
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
4 of 16
PHILIPS [ NXP SEMICONDUCTORS ]
