NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5. Pinning information
5.1 Pinning
1RD
2
3
4
5
6
7
GND
2Q
8
1
1D
1CP
1SD
1Q
1Q
GND
2
3
4
5
6
7
001aad106
1RD
1
14 V
CC
13 2RD
12 2D
terminal 1
index area
1D
1CP
1SD
1Q
14 V
CC
13 2RD
12 2D
11 2CP
10 2SD
9
2Q
74
11 2CP
10 2SD
74
GND
(1)
1Q
9
8
2Q
2Q
001aad107
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration for SO14 and (T)SSOP14
Fig 6. Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
complement output
true output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
74LVC74A_6
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 — 4 June 2007
3 of 16
PHILIPS [ NXP SEMICONDUCTORS ]
