74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 06 — 4 June 2007
Product data sheet
1. General description
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs,
clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate independently of the
clock input. Information on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time
prior to the LOW-to-HIGH clock transition, for predictable operation.
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and
fall times.
2. Features
I
I
I
I
I
I
5 V tolerant inputs for interlacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
N
HBM JESD22-A114D exceeds 2000 V
N
CDM JESD22-C101C exceeds 1000 V
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to 125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC74AD
74LVC74ADB
−40 °C
to +125
°C
−40 °C
to +125
°C
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
74LVC74APW
−40 °C
to +125
°C
74LVC74ABQ
−40 °C
to +125
°C
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
PHILIPS [ NXP SEMICONDUCTORS ]
