Philips Semiconductors
Product specification
8-bit serial-in, serial or parallel-out shift
register with output latches; 3-state
Family 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
TEST CONDITIONS
SYMBOL
T
amb
= 25
°C
t
PHL
/t
PLH
propagation delay
SH_CP to Q7’
propagation delay
ST_CP to Qn
t
PHL
t
PZH
/t
PZL
t
PHZ
/t
PLZ
t
W
propagation delay
MR to Q7’
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
shift clock pulse width
HIGH or LOW
storage clock pulse width
HIGH or LOW
master reset pulse width
LOW
t
su
set-up time DS to SH_CP
set-up time
SH_CP to ST_CP
t
h
t
rem
f
max
hold time DS to SH_CP
removal time
MR to SH_CP
maximum clock
pulse frequency
SH_CP or ST_CP
see Fig.7
see Fig.8
see Fig.10
see Fig.11
see Fig.11
see Fig.7
see Fig.8
see Fig.10
see Fig.9
see Fig.8
see Fig.9
see Fig.10
see Figs 7 and 8
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
−
−
−
−
−
16
16
20
16
16
+3
+10
30
PARAMETER
WAVEFORMS
V
CC
(V)
74HC595; 74HCT595
MIN.
TYP.
MAX.
UNIT
25
24
23
21
18
6
5
8
5
8
−2
−7
52
42
40
40
35
30
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
T
amb
=
−40
to +85
°C
t
PHL
/t
PLH
propagation delay
SH_CP to Q7’
propagation delay
ST_CP to Qn
t
PHL
t
PZH
/t
PZL
t
PHZ
/t
PLZ
propagation delay
MR to Q7’
3-state output enable time
OE to Qn
3-state output disable time
OE to Qn
see Fig.7
see Fig.8
see Fig.10
see Fig.11
see Fig.11
4.5
4.5
4.5
4.5
4.5
−
−
−
−
−
−
−
−
−
−
53
50
50
44
38
ns
ns
ns
ns
ns
2003 Jun 25
17
PHILIPS [ NXP SEMICONDUCTORS ]
