M58LT256JST, M58LT256JSB
Common Flash interface
Table 42. Bank and erase block region information
M58LT256JST M58LT256JSB
Description
Offset
Data
Offset
Data
(P+23)h = 12Dh 02h (P+23)h = 12Dh
02h Number of bank regions within the device
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
Table 43. Bank and erase block region 1 information
M58LT256JST
Offset Data
M58LT256JSB
Offset Data
Description
(P+24)h = 12Eh 0Fh (P+24)h = 12Eh 01h
(P+25)h = 12Fh 00h (P+25)h = 12Fh 00h
Number of identical banks within bank region 1
Number of program or erase operations allowed in
bank region 1:
Bits 0-3: number of simultaneous program
operations
(P+26)h = 130h 11h (P+26)h = 130h 11h
Bits 4-7: number of simultaneous erase
operations
Number of program or erase operations allowed in
other banks while a bank in same region is
programming
(P+27)h = 131h 00h (P+27)h = 131h 00h Bits 0-3: number of simultaneous program
operations
Bits 4-7: number of simultaneous erase
operations
Number of program or erase operations allowed in
other banks while a bank in this region is erasing
Bits 0-3: number of simultaneous program
(P+28)h = 132h 00h (P+28)h = 132h 00h
operations
Bits 4-7: number of simultaneous erase
operations
Types of erase block regions in bank region 1
n = number of erase block regions with contiguous
(P+29)h = 133h 01h (P+29)h = 133h 02h same-size erase blocks.
Symmetrically blocked banks have one blocking
region(2)
.
(P+2A)h = 134h 0Fh (P+2A)h = 134h 03h
(P+2B)h = 135h 00h (P+2B)h = 135h 00h
(P+2C)h = 136h 00h (P+2C)h = 136h 80h
(P+2D)h = 137h 02h (P+2D)h = 137h 00h
(P+2E)h = 138h 64h (P+2E)h = 138h 64h
(P+2F)h = 139h 00h (P+2F)h = 139h 00h
Bank Region 1 Erase Block Type 1 Information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n×256 = number of bytes in erase
block region
Bank region 1 (Erase Block Type 1)
Minimum block erase cycles × 1000
85/108