Common Flash interface
M58LT256JST, M58LT256JSB
Table 44. Bank and erase block region 2 information (continued)
M58LT256JST M58LT256JSB
Description
Offset
Data
Offset
Data
(P+40)h = 14Ah 03h
(P+41)h = 14Bh 00h
(P+42)h = 14Ch 80h
(P+43)h = 14Dh 00h
(P+44)h = 14Eh 64h
(P+45)h = 14Fh 00h
Bank region 2 Erase Block type 2 information
Bits 0-15: n+1 = number of identical-sized erase
blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
Bank region 2 (Erase Block type 2)
Minimum block erase cycles × 1000
Bank region 2 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+46)h = 150h 02h
Bank region 2 (Erase Block type 2): page mode
and synchronous mode capabilities (defined in
Table 41)
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
(P+47)h = 151h 03h
(P+48)h = 152h
(P+49)h = 153h
(P+48)h = 152h
(P+43)h = 153h
Feature space definitions
Reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
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