Common Flash interface
M58LT256JST, M58LT256JSB
Description
Table 43. Bank and erase block region 1 information (continued)
M58LT256JST
Offset Data
M58LT256JSB
Offset Data
Bank region 1 (Erase Block type 1): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+30)h = 13Ah 02h (P+30)h = 13Ah 02h
Bank region 1 (Erase Block type 1): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
(P+31)h = 13Bh 03h (P+31)h = 13Bh 03h
(P+32)h = 13Ch 0Eh Bank region 1 Erase Block type 2 information
(P+33)h = 13Dh 00h
(P+34)h = 13Eh 00h
Bits 0-15: n+1 = number of identical-sized
erase blocks
Bits 16-31: n × 256 = number of bytes in erase
block region
(P+35)h = 13Fh 02h
(P+36)h = 140h 64h
(P+37)h = 141h 00h
Bank region 1 (Erase Block type 2)
Minimum block erase cycles × 1000
Bank regions 1 (Erase Block Type 2): bits per cell,
internal ECC
Bits 0-3: bits per cell in erase region
Bit 4: reserved for “internal ECC used”
Bits 5-7: reserved
(P+38)h = 142h 02h
(P+39)h = 143h 03h
Bank region 1 (Erase Block Type 2): page mode
and synchronous mode capabilities
Bit 0: page-mode reads permitted
Bit 1: synchronous reads permitted
Bit 2: synchronous writes permitted
Bits 3-7: reserved
1. The variable P is a pointer which is defined at CFI offset 015h.
2. Bank regions. There are two bank regions, see Tables 29 to 34.
3. Although the device supports Page Read mode, this is not described in the datasheet as its use is not
advantageous in a multiplexed device.
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