DC and AC parameters
M58LT256JST, M58LT256JSB
(1)
Table 25. Write AC characteristics, Chip Enable controlled
M58LT256JST/B
85
Symbol
Alt
Parameter
Unit
tAVAV
tAVEH
tAVLH
tDVEH
tEHAX
tEHDX
tEHEL
tEHGL
tEHWH
tELKV
tELEH
tELLH
tELQV
tGHEL
tLHAX
tLLLH
tWC Address Valid to Next Address Valid
Address Valid to Chip Enable High
Address Valid to Latch Enable High
tDS Data Valid to Chip Enable High
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
50
10
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAH
Chip Enable High to Address Transition
tDH Chip Enable High to Input Transition
tCPH Chip Enable High to Chip Enable Low
Chip Enable High to Output Enable Low
tCH Chip Enable High to Write Enable High
Chip Enable Low to Clock Valid
0
25
0
0
9
tCP Chip Enable Low to Chip Enable High
Chip Enable Low to Latch Enable High
Chip Enable Low to Output Valid
50
10
85
17
9
Output Enable High to Chip Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
10
25
0
(2)
tWHEL
tWLEL
tEHVPL
tQVVPL
Write Enable High to Chip Enable Low
tCS Write Enable Low to Chip Enable Low
Chip Enable High to VPP Low
200
0
Output (Status Register) Valid to VPP Low
tVPHEH
tVPS VPP High to Chip Enable High
Min
200
ns
1. Sampled only, not 100% tested.
2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration
Register command. System designers should take this into account and may insert a software No-Op
instruction to delay the first read in the same bank after issuing any command and to delay the first read to
any address after issuing a Set Configuration Register command. If the first read after the command is a
Read Array operation in a different bank and no changes to the Configuration Register have been issued,
t
WHEL is 0 ns.
68/108
NUMONYX [ NUMONYX B.V ]
