DC and AC parameters
M58LT256JST, M58LT256JSB
(1)
Table 24. Write AC characteristics, Write Enable controlled
M58LT256JST/B Unit
85
Symbol Alt Parameter
tAVAV
tAVLH
tWC Address Valid to Next Address Valid
Address Valid to Latch Enable High
Address Valid to Write Enable High
tDS Data Valid to Write Enable High
Chip Enable Low to Latch Enable High
tCS Chip Enable Low to Write Enable Low
Chip Enable Low to Output Valid
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
85
10
50
50
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(3)
tAVWH
tDVWH
tELLH
tELWL
tELQV
tELKV
tGHWL
tLHAX
tLLLH
85
9
Chip Enable Low to Clock Valid
Output Enable High to Write Enable Low
Latch Enable High to Address Transition
Latch Enable Pulse Width
17
9
10
0
(2)
tWHAV
Write Enable High to Address Valid
tAH Write Enable High to Address Transition
tDH Write Enable High to Input Transition
tCH Write Enable High to Chip Enable High
Write Enable High to Chip Enable Low
Write Enable High to Output Enable Low
Write Enable High to Latch Enable Low
(2)
tWHAX
tWHDX
tWHEH
0
0
0
(3)
tWHEL
tWHGL
25
0
(3)
tWHLL
25
25
50
0
tWHWL tWPH Write Enable High to Write Enable Low
tWLWH
tQVVPL
tWP Write Enable Low to Write Enable High
Output (Status Register) Valid to VPP Low
tVPHWH tVPS VPP High to Write Enable High
200
tWHVPL
Write Enable High to VPP Low
Min
200
ns
1. Sampled only, not 100% tested.
2. Meaningful only if L is always kept Low.
3. tWHEL and tWHLL have this value when reading in the targeted bank or when reading following a Set
Configuration Register command. System designers should take this into account and may insert a
software No-Op instruction to delay the first read in the same bank after issuing any command and to
delay the first read to any address after issuing a Set Configuration Register command. If the first read
after the command is a Read Array operation in a different bank and no changes to the Configuration
Register have been issued, tWHEL and tWHLL are 0 ns.
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