M58LT256JST, M58LT256JSB
Read modes
7.2
Synchronous burst read mode
In synchronous burst read mode the data is output in bursts synchronized with the clock. It is
possible to perform burst reads across bank boundaries.
Synchronous burst read mode can only be used to read the memory array. For other read
operations, such as read Status Register, read CFI and read electronic signature, single
synchronous read or asynchronous random access read must be used.
In synchronous burst read mode the flow of the data output depends on parameters that are
configured in the Configuration Register.
A burst sequence starts at the first clock edge (rising or falling depending on valid clock
edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip
Enable, whichever occurs last. Addresses are internally incremented and data is output on
each data cycle after a delay which depends on the X latency bits CR13-CR11 of the
Configuration Register.
The number of words to be output during a synchronous burst read operation can be
configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The
data can be configured to remain valid for one or two clock cycles (data output configuration
bit CR9).
The order of the data output can be modified through the wrap burst bit in the Configuration
Register. The burst sequence is sequential and can be confined inside the 4 or 8-word
boundary (wrap) or overcome the boundary (no wrap).
The WAIT signal may be asserted to indicate to the system that an output delay is occurring.
This delay depends on the starting address of the burst sequence and on the burst
configuration.
WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16-word
burst. It is only de-asserted when output data is valid. In continuous burst read mode a
WAIT state occurs when crossing the first 16-word boundary. If the starting address is
aligned to the burst length (4, 8 or 16 words), the wrapped configuration has no impact on
the output sequence.
The WAIT signal can be configured to be active Low or active High by setting CR10 in the
Configuration Register.
See Table 23: Synchronous read AC characteristics and Figure 11: Synchronous burst read
AC waveforms for details.
7.2.1
Synchronous burst read suspend
A synchronous burst read operation can be suspended, freeing the data bus for other higher
priority devices. It can be suspended during the initial access latency time (before data is
output) or after the device has output data. When the synchronous burst read operation is
suspended, internal array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as required as long as
the operating conditions of the device are met.
A synchronous burst read operation is suspended when Chip Enable, E, is Low and the
current address has been latched (on a Latch Enable rising edge or on a valid clock edge).
The Clock signal is then halted at V or at V , and Output Enable, G, goes High.
IH
IL
When Output Enable, G, becomes Low again and the Clock signal restarts, the
synchronous burst read operation is resumed exactly where it stopped.
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