Read modes
M58LT256JST, M58LT256JSB
WAIT being gated by E, it remains active and does not revert to high impedance when G
goes High. So if two or more devices are connected to the system’s READY signal, to
prevent bus contention the WAIT signal of the M58LT256JST/B should not be directly
connected to the system’s READY signal.
WAIT reverts to high-impedance when Chip Enable, E, goes High.
See Table 23: Synchronous read AC characteristics and Figure 13: Synchronous burst read
suspend AC waveforms for details.
7.3
Single synchronous read mode
Single synchronous read operations are similar to synchronous burst read operations,
except that the memory outputs the same data to the end of the operation.
Synchronous single reads are used to read the electronic signature, Status Register, CFI,
block protection status, Configuration Register status or Protection Register. When the
addressed bank is in read CFI, read Status Register or read electronic signature mode, the
WAIT signal is asserted during the X latency and at the end of a 4, 8 and 16-word burst. It is
only de-asserted when output data are valid.
See Table 23: Synchronous read AC characteristics and Figure 11: Synchronous burst read
AC waveforms for details.
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