M58LT256JST, M58LT256JSB
Configuration Register
Table 11. Configuration Register
Bit
Description
Read select
Reserved
Value
Description
0
Synchronous read
CR15
CR14
1
Asynchronous read (default at power-on)
010
011
100
101
110
111
2 clock latency(1)
3 clock latency
4 clock latency
CR13-CR11 X latency
5 clock latency
6 clock latency
7 clock latency (default)
Other configurations reserved
0
1
0
1
0
WAIT is active Low
CR10
CR9
Wait polarity
WAIT is active High (default)
Data held for one clock cycle
Data held for two clock cycles (default)(1)
WAIT is active during WAIT state
Data output configuration
CR8
Wait configuration
WAIT is active one data cycle before WAIT
state(1) (default)
1
0
1
0
1
Reserved
CR7
CR6
Burst type
Sequential (default)
Falling Clock edge
Rising Clock edge (default)
Valid clock edge
CR5-CR4 Reserved
CR3 Wrap burst
0
Wrap
1
No wrap (default)
4 words
001
010
111
CR2-CR0 Burst length
8 words
Continuous (default)
1. The combination X latency=2, Data held for two clock cycles and Wait active one data cycle before the
WAIT state is not supported.
41/108
NUMONYX [ NUMONYX B.V ]
