M58LT256JST, M58LT256JSB
Dual operations and multiple bank architecture
8
Dual operations and multiple bank architecture
The multiple bank architecture of the M58LT256JST/B gives greater flexibility for software
developers to split the code and data spaces within the memory array. The dual operations
feature simplifies the software management of the device by allowing code to be executed
from one bank while another bank is being programmed or erased.
The dual operations feature means that while programming or erasing in one bank, read
operations are possible in another bank with zero latency (only one bank at a time is allowed
to be in program or erase mode).
If a read operation is required in a bank, which is programming or erasing, the program or
erase operation can be suspended. Also if the suspended operation is erase, then a
program command can be issued to another block. This means the device can have one
block in erase suspend mode, one programming, and other banks in read mode.
Bus read operations are allowed in another bank between setup and confirm cycles of
program or erase operations.
By using a combination of these features, read operations are possible at any moment in the
M58LT256JST/B device.
Dual operations between the parameter bank and either of the CFI, the OTP or the
electronic signature memory space are not allowed. Table 15 shows which dual operations
are allowed or not between the CFI, the OTP, the electronic signature locations and the
memory array.
Tables 13 and 14 show the dual operations possible in other banks and in the same bank.
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