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M29W400DT70ZA1 参数 Datasheet PDF下载

M29W400DT70ZA1图片预览
型号: M29W400DT70ZA1
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512 KB ×8或256 KB ×16 ,引导块) 3 V电源闪存 [4 Mbit (512 Kb x 8 or 256 Kb x 16, boot block) 3 V supply Flash memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1025 K
品牌: NUMONYX [ NUMONYX B.V ]
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Bus operations  
M29W400DT, M29W400DB  
3
Bus operations  
There are five standard bus operations that control the device. These are Bus Read, Bus  
Write, Output Disable, Standby and Automatic Standby. See Table 2 and Table 3, Bus  
operations, for a summary. Typically glitches of less than 5 ns on Chip Enable or Write  
Enable are ignored by the memory and do not affect bus operations.  
3.1  
Bus Read  
Bus Read operations read from the memory cells, or specific registers in the command  
interface. A valid Bus Read operation involves setting the desired address on the Address  
inputs, applying a Low signal, V , to Chip Enable and Output Enable and keeping Write  
IL  
Enable High, V . The Data inputs/outputs will output the value, see Figure 11: Read mode  
IH  
AC waveforms, and Table 12: Read AC characteristics, for details of when the output  
becomes valid.  
3.2  
Bus Write  
Bus Write operations write to the command interface. A valid Bus Write operation begins by  
setting the desired address on the Address inputs. The Address inputs are latched by the  
command interface on the falling edge of Chip Enable or Write Enable, whichever occurs  
last. The Data inputs/outputs are latched by the command interface on the rising edge of  
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V ,  
IH  
during the whole Bus Write operation. See Figure 12 and Figure 13, Write AC waveforms,  
and Table 13 and Table 14, Write AC characteristics, for details of the timing requirements.  
3.3  
3.4  
Output Disable  
The Data inputs/outputs are in the high impedance state when Output Enable is High, V .  
IH  
Standby  
When Chip Enable is High, V , the memory enters Standby mode and the Data  
IH  
inputs/outputs pins are placed in the high-impedance state. To reduce the Supply current to  
the Standby Supply current, I  
, Chip Enable should be held within V  
0.2 V. For the  
CC2  
CC  
Standby current level see Table 11: DC characteristics.  
During program or erase operations the memory will continue to use the Program/Erase  
Supply current, I , for Program or Erase operations until the operation completes.  
CC3  
3.5  
Automatic Standby  
If CMOS levels (V  
0.2 V) are used to drive the bus and the bus is inactive for 150 ns or  
CC  
more the memory enters Automatic Standby where the internal Supply current is reduced to  
the Standby Supply current, I  
operation is in progress.  
. The Data inputs/outputs will still output data if a Bus Read  
CC2  
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