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M29W400DT70ZA1 参数 Datasheet PDF下载

M29W400DT70ZA1图片预览
型号: M29W400DT70ZA1
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512 KB ×8或256 KB ×16 ,引导块) 3 V电源闪存 [4 Mbit (512 Kb x 8 or 256 Kb x 16, boot block) 3 V supply Flash memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1025 K
品牌: NUMONYX [ NUMONYX B.V ]
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M29W400DT, M29W400DB  
Signal descriptions  
2
Signal descriptions  
See Figure 1: Logic diagram, and Table : , for a brief overview of the signals connected to  
this device.  
2.1  
2.2  
2.3  
Address inputs (A0-A17)  
The Address inputs select the cells in the memory array to access during Bus Read  
operations. During Bus Write operations they control the commands sent to the command  
interface of the Program/Erase controller.  
Data inputs/outputs (DQ0-DQ7)  
The Data inputs/outputs output the data stored at the selected address during a Bus Read  
operation. During Bus Write operations they represent the commands sent to the command  
interface of the Program/Erase controller.  
Data inputs/outputs (DQ8-DQ14)  
The Data inputs/outputs output the data stored at the selected address during a Bus Read  
operation when BYTE is High, V . When BYTE is Low, V , these pins are not used and are  
IH  
IL  
high impedance. During Bus Write operations the Command Register does not use these  
bits. When reading the Status Register these bits should be ignored.  
2.4  
Data input/output or Address input (DQ15A-1)  
When BYTE is High, V , this pin behaves as a Data input/output pin (as DQ8-DQ14). When  
IH  
BYTE is Low, V , this pin behaves as an address pin; DQ15A–1 Low will select the LSB of  
IL  
the word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text  
consider references to the Data input/output to include this pin when BYTE is High and  
references to the Address inputs to include this pin when BYTE is Low except when stated  
explicitly otherwise.  
2.5  
2.6  
Chip Enable (E)  
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to  
be performed. When Chip Enable is High, V , all other pins are ignored.  
IH  
Output Enable (G)  
The Output Enable, G, controls the Bus Read operation of the memory.  
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