M29W128GH, M29W128GL
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals
connected to this device.
2.1
2.2
2.3
Address inputs (A0-A22)
The Address inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the command
interface of the Program/Erase controller.
Data inputs/outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the command interface
of the internal state machine.
Data inputs/outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, V . When BYTE is Low, V , these pins are not used and are high
IH
IL
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
2.4
Data inputs/outputs or address inputs (DQ15A−1)
When the device is in x 16 bus mode, this pin behaves as a Data input/output pin (as DQ8-
DQ14). When the device operates in x 8 bus mode, this pin behaves as the least significant
bit of the address. Throughout the text consider references to the Data input/output to
include this pin when the device operates in x 16 bus mode and references to the Address
inputs to include this pin when the device operates in x 8 bus mode except when stated
explicitly otherwise.
2.5
2.6
Chip Enable (E)
The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations
to be performed. When Chip Enable is High, V , all other pins are ignored.
IH
Output Enable (G)
The Output Enable pin, G, controls the Bus Read operation of the memory.
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NUMONYX [ NUMONYX B.V ]
