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M29W128GH70N6E 参数 Datasheet PDF下载

M29W128GH70N6E图片预览
型号: M29W128GH70N6E
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位( Mb的16 ×8或8MB ×16 ,页,均匀的块) 3 V电源闪存 [128 Mbit (16 Mb x 8 or 8 Mb x 16, page, uniform block) 3 V supply Flash memory]
分类和应用: 闪存
文件页数/大小: 94 页 / 1789 K
品牌: NUMONYX [ NUMONYX B.V ]
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M29W128GH, M29W128GL  
Signal descriptions  
2.9  
Reset (RP)  
The Reset pin can be used to apply a Hardware Reset to the memory.  
A Hardware Reset is achieved by holding Reset Low, V , for at least t  
. After Reset goes  
PLPX  
IL  
High, V , the memory will be ready for Bus Read and Bus Write operations after t  
or  
IH  
PHEL  
t
, whichever occurs last. See Section 2.10: Ready/Busy output (RB), Table 29: Reset  
RHEL  
AC characteristics, Figure 21 and Figure 22 for more details.  
2.10  
Ready/Busy output (RB)  
The Ready/Busy pin is an open-drain output that can be used to identify when the device is  
performing a program or erase operation. During program or erase operations Ready/Busy  
is Low, V (see Table 20: Status Register bits). Ready/Busy is high-impedance during  
OL  
Read mode, Auto Select mode and Erase Suspend mode.  
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy  
becomes high-impedance. See Table 29: Reset AC characteristics, Figure 21 and  
Figure 22.  
The use of an open-drain output allows the Ready/Busy pins from several memories to be  
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the  
memories is busy.  
2.11  
2.12  
Byte/word organization select (BYTE)  
It is used to switch between the x 8 and x 16 Bus modes of the memory. When Byte/word  
organization select is Low, V , the memory is in x 8 mode, when it is High, V , the memory  
IL  
IH  
is in x 16 mode.  
VCC supply voltage  
V
provides the power supply for all operations (Read, Program and Erase).  
CC  
The command interface is disabled when the V supply voltage is less than the Lockout  
CC  
voltage, V  
. This prevents Bus Write operations from accidentally damaging the data  
LKO  
during power-up, power-down and power surges. If the Program/Erase controller is  
programming or erasing during this time then the operation aborts and the memory contents  
being altered will be invalid.  
A 0.1 µF capacitor should be connected between the V supply voltage pin and the V  
CC  
SS  
ground pin to decouple the current surges from the power supply. The PCB track widths  
must be sufficient to carry the currents required during program and erase operations (see  
I
, I  
, I  
in Table 25: DC characteristics).  
CC1 CC2 CC3  
2.13  
VCCQ input/output supply voltage  
V
provides the power supply to the I/O pins and enables all outputs to be powered  
CCQ  
independently from V  
.
CC  
15/94