M29W128GH, M29W128GL
Table 2.
Signal names
Name
A0-A22
DQ0-DQ7
DQ8-DQ14
DQ15A−
1
E
G
W
RP
RB
BYTE
V
CCQ
V
CC
V
PP
/WP
(1)
V
SS
NC
Address inputs
Data inputs/outputs
Data inputs/outputs
Data input/output or address input
Chip Enable
Output Enable
Write Enable
Reset
Ready/Busy output
Byte/word organization select
Input/output buffer supply voltage
Supply voltage
V
PP
/Write Protect
Ground
Not connected
Description
Description
Direction
Inputs
I/O
I/O
I/O
Input
Input
Input
Input
Output
Input
Supply
Supply
Input
-
-
1. V
PP
/WP may be left floating as it is internally connected to a pull-up resistor which enables Program/Erase
operations.
Figure 1.
Logic diagram
VCC VCCQ VPP/WP
23
A0-A22
W
E
G
RP
BYTE
M29W128GH
M29W128GL
15
DQ0-DQ14
DQ15A-1
RB
VSS
AI13330b
1. Also see
and
for a full listing of the block addresses.
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