M25PE80
Operating features
4.8.2
Specific hardware and software protections
The M25PE80 features a hardware protected mode, HPM, and two software protected
modes, SPM1 and SPM2, that can be combined to protect the memory array as required.
They are described below:
HPM
■
HPM in T7Y process (see Important note on page 6):
The hardware protected mode (HPM) is entered when top sector lock (TSL) is driven
Low, causing the top 256 pages of memory to become read-only. When top sector lock
(TSL) is driven High, the top 256 pages of memory behave like the other pages of
memory and the protection depends on the block protect bits (see SPM2 below).
■
HPM in T9HX process (see Important note on page 6):
The hardware protected mode (HPM) is used to write-protect the non-volatile bits of the
status register (that is, the block protect bits, BP2, BP1 and BP0, and the status register
write disable bit, SRWD).
HPM is entered by driving the Write Protect (W) signal Low with the SRWD bit set to
High. This additional protection allows the status register to be hardware-protected.
(see also Section 6.4.4: SRWD bit).
SPM1 and SPM2
■
The first software protected mode (SPM1) is managed by specific lock registers
assigned to each 64-Kbyte sector.
The lock registers can be read and written using the read lock register (RDLR) and
write to lock register (WRLR) instructions.
In each lock register two bits control the protection of each sector: the write lock bit and
the lock down bit.
–
Write lock bit:
The write lock bit determines whether the contents of the sector can be modified
(using the write, program or erase instructions). When the write lock bit is set to ‘1’,
the sector is write protected – any operations that attempt to change the data in
the sector will fail. When the write lock bit is reset to ‘0’, the sector is not write
protected by the lock register, and may be modified.
–
Lock down bit:
The lock down bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the lock down bit is set to ‘1’, further
modification to the write lock and lock down bits cannot be performed. A reset, or
power-up, is required before changes to these bits can be made. When the lock
down bit is reset, ‘0’, the write lock and lock down bits can be changed.
The write lock bit and the lock down bit are volatile and their value is reset to ‘0’ after a
power-down or a reset.
The definition of the lock register bits is given in Table 11: Not for new design: lock
registers for the M25PE80 in T7Y process.
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