欢迎访问ic37.com |
会员登录 免费注册
发布采购

M25P10-AVMB6TP/Y 参数 Datasheet PDF下载

M25P10-AVMB6TP/Y图片预览
型号: M25P10-AVMB6TP/Y
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位,串行闪存, 50MHz的SPI总线接口 [1 Mbit, serial Flash memory, 50 MHz SPI bus interface]
分类和应用: 闪存存储内存集成电路时钟
文件页数/大小: 51 页 / 989 K
品牌: NUMONYX [ NUMONYX B.V ]
 浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第36页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第37页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第38页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第39页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第41页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第42页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第43页浏览型号M25P10-AVMB6TP/Y的Datasheet PDF文件第44页  
DC and AC parameters  
M25P10-A  
Table 18. AC characteristics (25 MHz operation, device grade 6 or 3)  
Test conditions specified in Table 10 and Table 12  
Symbol  
Alt.  
Parameter  
Min  
Typ  
Max  
Unit  
Clock frequency for the following  
fC  
fR  
fC  
instructions: FAST_READ, PP, SE, BE, DP,  
RES, WREN, WRDI, RDSR, WRSR  
D.C.  
25  
20  
MHz  
Clock frequency for READ instructions  
D.C.  
18  
18  
0.1  
0.1  
10  
10  
5
MHz  
ns  
(1)  
tCH  
tCLH Clock High time  
tCLL Clock Low time  
(1)  
tCL  
ns  
(2)  
tCLCH  
Clock Rise time(3) (peak to peak)  
V/ns  
V/ns  
ns  
(2)  
tCHCL  
Clock Fall time(3) (peak to peak)  
tCSS S Active Setup time (relative to C)  
S Not Active Hold time (relative to C)  
tDSU Data In Setup time  
tSLCH  
tCHSL  
tDVCH  
tCHDX  
tCHSH  
tSHCH  
tSHSL  
ns  
ns  
tDH  
Data In Hold time  
5
ns  
S Active Hold time (relative to C)  
S Not Active Setup time (relative to C)  
10  
10  
100  
ns  
ns  
tCSH S Deselect time  
ns  
(2)  
tSHQZ  
tDIS  
tV  
Output Disable time  
15  
15  
ns  
tCLQV  
tCLQX  
tHLCH  
tCHHH  
tHHCH  
tCHHL  
Clock Low to Output Valid  
Output Hold time  
ns  
tHO  
0
ns  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
HOLD Setup time (relative to C)  
HOLD Hold time (relative to C)  
HOLD to Output Low-Z  
10  
10  
10  
10  
ns  
ns  
ns  
ns  
(2)  
tHHQX  
tLZ  
15  
20  
ns  
(2)  
tHLQZ  
tHZ  
HOLD to Output High-Z  
ns  
(4)  
tWHSL  
Write Protect Setup time  
Write Protect Hold time  
20  
ns  
(4)  
tSHWL  
100  
ns  
(2)  
tDP  
S High to Deep Power-down mode  
3
µs  
S High to Standby mode without Read  
Electronic Signature  
(2)  
tRES1  
3 or 30(5)  
µs  
µs  
S High to Standby mode with Read  
Electronic Signature  
tRES2  
1.8 or 30(5)  
(2)  
1. tCH + tCL must be greater than or equal to 1/ fC.  
2. Value guaranteed by characterization, not 100% tested in production.  
3. Expressed as a slew-rate.  
4. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.  
5. It is 30 µs in devices produced with the ‘X’ and ‘Y’ process technology (grade 3 devices are only produced  
using the ‘X’ process technology). Details of how to find the process letter on the device marking are given  
in the application note AN1995.  
40/51  
 复制成功!